Air bag systems are commonly used in automotive applications to provide protection for the vehicle operator and/or passengers in the vehicle in the event of a vehicular collision. Known techniques for implementing an air bag system in a vehicle generally include detecting vehicular deceleration via an accelerometer (i.e., acceleration sensor). The accelerometer generates an analog output signal that is processed to determine if an impact of sufficient severity has occurred to require deployment of one or more air bags in the vehicle.
Various types of accelerometers are known, some of which include piezo-resistive sensors, typically micro-machined, that produce a differential analog output voltage proportional to the applied acceleration (or deceleration).
Applications that employ accelerometers typically include signal conditioning circuitry for amplifying the sensor generated analog output signal and compensating for gain and offset to account for temperature variations and manufacturing tolerance variations. Some conventional signal conditioning circuitry for accelerometers employed in vehicle air bag systems may require a gain of approximately 250, according to one example, to produce sufficient amplitude acceleration signals that may be used to discriminate a vehicle collision using analog-to-digital converters present in many microprocessors. Additionally, in order to determine valid impact discrimination, the output offset generated by the sensor and processed by any associated signal conditioning circuitry typically is required to be less than 20 millivolts. Typical automotive applications operate throughout a temperature range of about −40° to +125° Celsius, which requires the signal offset variation to be less than about 0.5 microvolts per degree Celsius.
Numerous techniques have been devised for minimizing offset in sensor generated analog signals employed in vehicle air bag systems. One such technique for minimizing offset in an analog signal is disclosed in U.S. Pat. No. 6,426,663, entitled “ANALOG/DIGITAL FEEDBACK CIRCUITRY FOR MINIMIZING DC OFFSET VARIATIONS IN AN ANALOG SIGNAL”, which is hereby incorporated herein by reference. The approach disclosed in the aforementioned U.S. patent employs a combination analog and digital feedback circuit coupled between the output and input of a gain stage amplifier. The feedback circuit employs a comparator, a clock circuit, and an up/down counter for slowly incrementing or decrementing a digital output signal that is converted to an analog signal via a digital-to-analog converter. The incrementally adjusted analog signal is applied to the input of the amplifier as a feedback signal to compensate for slowly varying DC offset.
While the aforementioned conventional feedback circuit offers significant advantages over prior analog integrator feedback circuits, a number of limitations do exist. First, the conventional feedback circuit is required to transition from an initial DC offset to the desired output value through a series of incremental values. For the conventional circuit to operate as designed, the analog output voltage signal must reach the final value before the next clock can transition the feedback signal. This results in a speed limitation in the analog signal limited by the maximum clock rate of the counter, which can cause a start up delay that delays the use of the sensor. Second, because the start up time is a function of the initial offset, the start up time becomes greater as the offset becomes greater. Third, the start up time can increase significantly, particularly if filter bandwidth is reduced. This is because the analog output voltage signal must be able to keep up with the feedback signal or the feedback signal may overshoot and not stop at the desired value. Fourth, the analog output signal generated by the conventional approach may not settle on a final value, as it continues to transition up and down around the desired center value. This results in a theoretical noise floor for the system that can limit system performance. Further, the decision to update the up/down counter in the prior approach is made at the rising edge of the clock. Spurious noise on the analog output signal at that critical instant could cause the comparator output to transition high or low when the average value is the opposite. This may cause the up/down counter to transition up and down and adversely impact noise on the system which makes it more difficult to predict the system impact.
Accordingly, it is therefore desirable to provide for a signal conditioning circuit for compensating for DC offset in an analog signal which eliminates or reduces limitations in the prior art. In particular, it is desirable to provide for a signal conditioning circuit having a feedback circuit that may quickly compensate for DC offset. Additionally, it is desirable to provide for a feedback circuit that compensates for DC offset in a manner that eliminates or reduces transitioning variations in the analog output signal.